a) Field of the Invention
The present invention relates to communications networks in general and in particular to circuits used to interconnect chips or modules of a communication system.
b) Prior Art
The ever-increasing requirement for higher performance and data throughput in networking and computing applications creates the need for Application Specific Integrated Circuits (ASICs) with higher numbers of physical input/output pins, or “I/Os”. Unfortunately ASIC packaging technology can implement only a finite number of I/Os. As the number of I/Os on an ASIC package is increased beyond a practical limit, it creates electrical and mechanical problems that degrade the performance and reliability of the ASIC.
In applications where the number of I/Os required exceeds the limits of ASIC packaging, the only option is to split what would have been a single ASIC into multiple ASIC chips. But splitting one ASIC chip into multiple ASICs chips often presents additional challenges with respect to the number of I/Os then required for communication between each of the ASICs in addition to the I/Os required by the originally intended external interfaces.
In view of the above circuits and method are required to interconnect chips without necessarily increasing the number of pins used in making such interconnections.